Abstract: Macro placement, which involves optimizing the positions of modules, is a critical phase in modern integrated circuit design and significantly influences chip performance. The growing complexity of integrated circuits demands increasingly sophisticated placement solutions. Existing approaches have evolved along two primary paths (e.g., constructive and adjustment methods), but they face significant practical limitations that affect real-world chip design. Recent hybrid frameworks such as WireMask-EA have attempted to combine these strategies, but significant technical barriers still remain, including the computational overhead from separated layout adjustment and reconstruction that often require complete layout rebuilding, the inefficient exploration of design spaces due to random mutation operations, and the computational complexity of mask-based construction methods that limit scalability. To overcome these limitations, we introduce EGPlace, a novel evolutionary optimization framework that combines guided mutation strategies with efficient layout reconstruction. EGPlace introduces two key innovations: a greedy repositioning-guided mutation operator that systematically identifies and optimizes critical layout regions, and an efficient mask computation algorithm that accelerates layout evaluation. Our extensive evaluation using ISPD2005 and Ariane RISC-V CPU benchmarks demonstrate that EGPlace reduces wirelength by \textbf{10.8\%} and \textbf{9.3\%} compared to WireMask-EA and the state-of-the-art reinforcement learning-based constructive method EfficientPlace, respectively, while achieving speedups of 7.8$\times$ and 2.8$\times$ over these methods.

Lay Summary:

The macro placement problem is an importance stage in designing modern computer chips. The task involves figuring out the best way to arrange large blocks on the chip. The way these blocks are placed can significantly affect the chip performance. The vast number of possible placement configurations makes macro placement a challenging task.Current methods for macro placement either construct layouts from scratch or iteratively refine existing ones. However, both approaches have drawbacks: they can involve high computational costs, lack sufficient contextual information to effectively guide placement decisions, or struggle to produce high-quality solutions. Some recent approaches combine these strategies by integrating a greedy placement technique within an evolutionary search framework, yet they still encounter challenges such as inefficient exploration caused by random mutations and slow computation due to the need to rebuild the entire layout even after minor adjustments.We introduce EGPlace, an efficient placement method that improves evolutionary search for chip layout by incorporating a novel guided mutation operator. This operator smartly selects a subset of blocks that have the greatest impact on layout quality and greedily repositions only those. It improves sample efficiency by increasing the likelihood of beneficial mutations, and reduce computational costs by avoiding the cost of rebuilding the entire layout. Experiments on modern circuit benchmarks show that EGPlace generates higher-quality layouts with up to 11% shorter wirelengths, while achieving up to 8× speedup over state-of-the-art methods.